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Power Supply IC Series for TFT-LCD Panels
12V Input Multi-channel System Power Supply IC
BD8166EFV
No.09035EBT14
Description The BD8166EFV is a system power supply for the TFT-LCD panels used for liquid crystal TVs. Incorporates two high-power FETs with low on resistance for large currents that employ high-power packages, thus driving large current loads while suppressing the generation of heat. A charge pump controller is incorporated as well, thus greatly reducing the number of application components. Features 1) Step-up and step-down DC/DC converter 2) Incorporates 2-A N-channel FET. 3) Incorporates positive/negative charge pumps. 4) Incorporates a gate shading function. 5) Input voltage limit: 6 V to 18 V 6) Feedback voltage: 1.25 V 1.6% 7) Switching frequency: 500 kHz 8) Protection circuit: Undervoltage lockout protection circuit Thermal shutdown circuit Overcurrent protection circuit Short protection circuit of timer latch type 9) HTSSOP-B40 Package Applications Power supply for the TFT-LCD panels used for LCD TVs Absolute maximum ratings (Ta = 25) Parameter Power supply voltage Vo1 voltage Vo2 voltage IG Voltage Maximum junction temperature Power dissipation Operating temperature range Storage temperature range
Symbol Vcc, PVCC Vo1 Vo2 IGH Tjmax Pd Topr Tstg
Limit 19 19 40 7 150 4700*1 -40 to 85 -55 to 150
Unit V V V V mW
* Reduced by 37.6 mW/ over 25, when mounted on a glass epoxy 4-layer board (70 mm 70 mm 1.6 mm) (Copper foil on back 70 mm 70 mm).
Recommended Operating Ranges (Ta = 25) Parameter Power supply voltage Vo1 voltage Vo2 voltage I G Voltage SW current Symbol VCC, PVCC Vo1 Vo2 IGH SW1, SW2 Limit Min. 6 8 -- -- -- Max. 18 18 39 5 2 Unit V V V V A
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1/17
2009.07 - Rev.B
BD81666EFV
Electrical characteristics (Unless otherwise specified, Ta = 25C, VCC = 15 V, Ta = 25) 1. DC/DC Converter Block Limit Parameter Symbol Unit Min. Typ. Max. [Soft start block SS1 and SS2] SS source current SS sinking current Clamp voltage [Error amp block FB1 and FB2] FB input bias current 1 and 2 Feedback voltage 1 and 2 Voltage gain COMP sinking current COMP source current [Switch output block SW1 and SW2] On resistance on high side On resistance on low side Off current Current limit Maximum duty ratio Ron h Ron l Ioff Insw DMax -- -- -- 2 -- 200 2 0.2 -- 97 300 3 -- -- -- m mA A % * Io = 1A* Io = 20 mA* IFB1, 2 VFB1, 2 AV IoI Ioo -- 1.230 -- 1 -12 0.4 1.250 200 2 -6 1.5 1.270 -- 4 -2 A V V/V mA mA VFB = 0.5 V Buffer Iso Isi Vcl 6 0.5 1.7 10 2 1.9 14 -- 2.1 A mA V Vss = 1.0 V Vss = 1.0 V
Technical Note
Conditions
VFB = 1.5 V, COMP = 1.5 V VFB = 1.0 V COMP = 1.0 V
2. Positive/Negative Charge Pump Block Parameter [Error amp block FB3 and FB4] Input bias current 3 Input bias current 4 Feedback voltage 3 Feedback voltage 4 [Delay start block SS3 and SS4] SS source current SS sinking current Startup voltage [Switch block C1L, C2L, and C3] N-channel on resistance P-channel on resistance RON_NC RON_PC -- -- 4 4 8 8 Io = 20 mA* Io = 20 mA* IDSO IDSI VST 3 0.2 0.52 5 0.5 0.65 7 -- 0.78 A mA V VDLS = 0.5 V VDLS = 0.5 V IFB3 IFB4 VFB3 VFB4 -- -- 1.18 1.18 0.1 0.1 1.25 1.25 0.5 0.5 1.32 1.32 A A V V Symbol Limit Min. Typ. Max. Unit Conditions
Design guarantee (No total shipment inspection is made.) *This product is not designed for protection against radio active rays.
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2/17
2009.07 - Rev.B
BD81666EFV
Electrical characteristics (Unless otherwise specified, Ta = 25, VCC = 15 V, Ta = 25) 3. Gate Shading Block Limit Parameter Symbol Unit Min. Typ. Max. [Output block Vo2GS and GSOUT] N-channel on resistance P-channel on resistance N-channel leak current P-channel leak current [Input block IG] IGH voltage IGL voltage IG sinking current 4. Overall Parameter [Reference voltage block VREF] Reference voltage Load stability [Regulator circuit block VREG] REG output voltage Load stability [Oscillator block] Frequency [Protection detection block FAULT] Off-leak current On resistance [Short protection block SCP] SCP lease current Threshold voltage Off sinking current [VCOM block] Input offset voltage Input bias current Drive current Slew rate GB product High output voltage Low output voltage [Low voltage protection circuit] Detection voltage [Overall] Average current consumption Icc 3.0 4.5 6.0 mA VUVLO 4.8 5.1 5.4 V Voso Ibo Ioo SRo GBW Voho Vohl -10 -- 50 5 -- Vol-0.3 -- 0 0.1 100 12 12 Vol-0.1 0.1 10 1 350 -- -- -- 0.3 mV A mA V/MS MHz V V Io = -5 mA Io = 5 mA Iscp Vth_scp IOFFS 6 0.96 1 10 1.2 3 14 1.44 -- A V mA SCP = 0.5 V IFL Ron_FL -- -- -- 1 10 -- A k Fosc 400 500 600 kHz VREG V 4.5 -- 5.0 50 5.5 100 V mV VREF V 2.84 -- 2.90 5 2.96 20 V mV IREF = 1 mA Symbol Limit Min. Typ. Max. Unit IGH LGL IIG 1.9 -- 8 2.9 0 16.5 5 0.9 25 V V A IG = 3.3 V Ron_NGS Ron_PGS ILEAK_NGS ILEAK_PGS -- -- -- -- 10 55 -- -- 15 80 10 10 A A Io = 20 mA* Io = 20 mA*
Technical Note
Conditions
Conditions
IREG = 10 mA
Standby current
Design guarantee (No total shipment inspection is made.) *This product is not designed for protection against radio active rays.
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3/17
2009.07 - Rev.B
BD81666EFV
Reference Data (Unless otherwise specified, Ta = 25)
8
6
.
Technical Note
60 50
CIRCUIT CURRENT : ICC[mA]
CIRCUITCURRENT : IVO1[mA]
.
6 25 4
85
85
STANDBY CURRENT : IVO2[A]
85 40 25 30 20 10 0 0 10 20 30 40
SUPPLY VOLTAGE : VO2[V]
4
25
-40
-40 2
2
-40
0 0 5 10 15 20 SUPPLY VOLTAGE : VCC [V]
0 0 5 10 15 20
SUPPLY VOLTAGE : VO1 [V]
Fig.1 Standby Circuit Current 1
Fig.2 Standby Circuit Current 2
Fig.3 Standby Circuit Current 3
4
4 25 3 -40 2 85
2.9 VREF29 VOLTAGE : VREF29[V]
40
.
VREF29 VOLTAGE : VREF29[V]
3
VREF29 VOLTAGE : VREF29[V]
2.8
2
-40
2.7
1
85 25
1
2.6
0 0 5 10 15 20
SUPPLY VOLT AGE : VCC[V]
0 0 10 20 30 VREF29 CURRENT : IREF29[mA]
2.5 -40 -50
-25
0
25
50
75
100
125
AMBIENT TEMPERATURE : Ta[]
Fig.4 Internal Reference Line Regulation
0.1 FB INPUT CURRENT : IFB1,2[A] 0 -0.1 -0.2 25 -0.3 -0.4 -40 -0.5 0 0.5 1 1.5 2 FB VOLTAGE : VFB1,2[V]
Fig.5 Internal Reference Load Regulation
1.6 FEEDBACK VOLTAGE : VFB1,2[V]
Fig.6 Internal Reference vs Temperature
100
85
DELAY TIME [ms]
1.2
10
0.8
1
0.4
0.1
0 0 5 10 15 20 SUPPLY VOLTAGE : VCC[V]
0.01 0.001
0.01
0.1
1
SS1,2 CAPACITOR [F]
Fig.7 DC/DC Error Amp Input Bias Current
120
Fig.8 DC/DC Error Amp Feedback Voltage
100
Fig.9 Soft Start Capacity vs Delay Time
600 SWITCHING FREQUENCY : f[kHz] .
SWITCHING Duty : Duty[%]
90
60 -40 30
25
DELAY TIME [ms]
85
550
10
500
1
450
0 0 0.4 0.8 1.2 1.6 COMP VOLTAGE : VCOMP1[V]
0.1 0.001
0.01 SS3,4 CAPACITOR[F]
0.1
400 -50
-25
0
25
50
75
100
AMBIENT TEMPERATURE : Ta []
Fig.10 Error Output Voltage vs Duty
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Fig.11 Delay Start Capacity vs Delay Time
Fig.12 Switching Frequency vs Temperature
4/17
2009.07 - Rev.B
BD81666EFV
Reference Data (Unless otherwise specified, Ta = 25)
100
Technical Note
1.6
OUTPUT VOLTAGE : VCOM[V]
20
INPUT CURRENT : IV+,IV-[uA]
1.2
15
25 85
. DELAY TIME[ms] 10
0.8
10
1
0.4
5
-40
0.1 0.001
0.01 SCP CAPACITOR[F]
0.1
0 0 5 10 15 20 25 INPUT VOLTAGE : V+,V- [V]
0 -300
-200
-100
0
100
200
300
OUTPUT CURRENT : ICOM[mA]
Fig.13 SCP Capacity vs Delay Time
1.6 OFFSET VOLTAGE : VOFFSET[mV]
Fig.14 COM Input Bias Current
Fig.15 COM Load Regulation
1.2
35V IG 15V
0.8
3.3V
0.4
Vo2GS
0 0 5 10 15 20 25 VCOM VOLTAGE : VCOM[V]
-6V
Fig.16 VCOM Offset Voltage
100 90 80 .
Fig.17 Start-up Sequence
100 90
TOTAL EFFICIENCY[%] .
Fig.18 Gate-shading Waveform
100
80 EFFICIENCY[%] 70 60 50 40 30 20 10
1000 OUTPUT CURRENT[mA] 10000
80
70 60 50 40 30 20 10 0 100
EFFICIENCY [%]
60
40
20
0 100
0
1000 OUTPUT CURRENT[mA]
10000
8
10
12
14
16
18
SUPPLY VOLTAGE[V]
Fig.19 Output Current vs Efficiency (Vo1)
400
140 120
Fig.20 Output Current vs Efficiency (VDD)
180 150 Cx VOLTAGE [mV] 120 90 60 30 0
0 20 40 60 80 100
Fig.21 Total Efficiency
320
Cx VOLTAGE [mV] 100 80 60 40 20 0
. VSW[mV] 240 160 80 0 0 200 400 600 800 1000 ISW[mA]
0
20
40
60
80
100
Cx CURRENT [mA]
Cx CURRENT [mA]
Fig.22 DC/DC SW On Resistance
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Fig.23 Charge Pump N-channel On Resistance
Fig.24 Charge Pump P-channel On Resistance
5/17
2009.07 - Rev.B
BD81666EFV
Pin Assignment Diagram Block Diagram
VDD
Technical Note
29
VCC
35
VREG
FAULT
11
VREG
CURRENT SENSE UVLO TSD FAULT LOGIC
36
PGND2 SW2 SW2 BOOT2 PVCC2 SS2 COMP2 FB2 SCP GND FAULT FB3 SS3 IG GSOUT Vo2 C1L C2L CPGND
PGND1 SW1 SW1 BOOT1 PVCC1 VREG SS1 COMP1 FB1 VREF29 SS4 VCC V V VCOM FB4 C3 Vo1
VREF29
31
VREF
OCP D
38
PVCC1 SW1
VIN 15V VO1
OSC SLOPE SOFT START
S R PWM R VREG
R V
39
SW1 PGND1 FB1 BOOT1
40
34
37
SS1
CURRENT SENSE ERR
FB1
32
5
PVCC2
OCP SD SW2
2 3
COMP1
33
R SOFT START SLOPE RV PWM VREG
VDD 3.3V/2A
SS2
6
SW2
1 4
PGND2 BOOT2 VO1 VO2 VGH FB2
FB2
8
ERR
23
COMP2
7
17
VO1 SS3
13
DELAY START POSITIVE CHARG PUMP
22
VO2
FB3
12
ERR
19
FB3 C2L C1L VO2GS VGH 36V/30mA With G/S
18
VGH
IG
CPGND
14
16
GATE SHADING CONTROLLER
15
GSOUT
FB4
25
ERR
NEGATIVE CHARGE PUMP
24
C3
VGL -9V/30mA
VCOM
26
VCOM
DELAY START
FB4 TIMER LATCH
VO1
27 28 30 10 20 21 9
VREF SCP
V-
V+
SS4
GND CPGND CPGND
Fig. 25 Pin Assignment Diagram & Block Diagram Pin Assignment and Pin Function Pin Pin Function No. name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PGND2 SW2 SW2 BOOT2 PVCC2 SS2 COMP2 FB2 SCP GND FAULT FB3 SS3 IG GSOUT Vo2GS Vo2 C1L C2L CPGND Ground pin Switching pin 2 Switching pin 2 Capacitance connection pin for booting 2 Power supply input pin Soft start capacitance connection pin 2 Error amp output 2 Feedback input 2 Capacitance connection pin for short protection delay Ground pin Protection detection output pin Feedback input 3 Delay start capacitance connection pin 3 Gate shading input pin Gate shading sink output pin Gate shading source output pin Power supply input pin Charge pump clock output 1 Charge pump clock output 2 Ground pin
Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Pin name CPGND VGH Vo1 C3 FB4 VCOM VV+ VCC SS4 VREF29 FB1 COMP1 SS1 VREG PVCC1 BOOT1 SW1 SW1 PGND1
Function Ground pin Positive charge pump diode connection pin Power supply input pin Charge pump clock output 3 Feedback input 3 VCOM output VCOM negative input pin VCOM positive input pin Power supply input pin Delay start capacitance connection pin 4 Standard voltage output pin Feedback input 1 Error amp output 1 Soft start capacitance connection pin 1 Regulator output pin for booting Power supply input pin Capacitance connection pin for booting 1 Switching pin 1 Switching pin 1 Ground pin
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6/17
2009.07 - Rev.B
BD81666EFV
Block Operation VREG A block to generate constant-voltage for DC/DC boosting. VREF A block that generates internal reference voltage of 2.9 V (Typ.).
Technical Note
TSD/UVLO TSD (Thermal shutdown)/UVLO (Under Voltage Lockout) protection block. The TSD circuit shuts down IC at 175C (Typ.) and recovers at 160C (Typ.). The UVLO circuit shuts down the IC when the Vcc is 5.1 V (Typ.) or below. Error amp block (ERR) This is the circuit to compare the reference voltage of 1.25 V (Typ.) and the feedback voltage of output voltage. The COMP pin voltage resulting from this comparison determines the switching duty. At the time of startup, since the soft start is operated by the SS pin voltage, the COMP pin voltage is limited to the SS pin voltage. Oscillator block (OSC) This block generates the oscillating frequency. SLOPE block This block generates the triangular waveform from the clock created by OSC. Generated triangular waveform is sent to the PWM comparator. PWM block The COMP pin voltage output by the error amp is compared to the SLOPE block's triangular waveform to determine the switching duty. Since the switching duty is limited by the maximum duty ratio which is determined internally, it does not become 100%. DRV block A DC/DC driver block. A signal from the PWM is input to drive the power FETs. CURRENT SENSE Current flowing to the power FET is detected by voltage at the CURRENT SENSE and the overcurrent protection operates at 3A (Typ.). When the overcurrent protection operates, switching is turned OFF and the SS pin capacitance is discharged. DELAY START A start delay circuit for positive/negative charge pump. Soft start circuit Since the output voltage rises gradually while restricting the current at the time of startup, it is possible to prevent the output voltage overshoot or the rush current. Positive charge pump A controller circuit for the positive-side charge pump. The switching amplitude is controlled so that the feedback voltage FB2 will be set to 1.25 V (Typ.). The start delay time can be set in the DLS pin at the time of startup. When the DLS voltage reaches 0.65 V (Typ.), switching waves will be output from the CL1 and CL2 pins. Negative charge pump A controller circuit for the negative-side charge pump. The switching amplitude is controlled so that the feedback voltage FB3 will be set to 1.25 V (Typ.). Gate shading controller A controller circuit of gate shading. The Vo2GS and GSOUT are turned on and off according to IG pin input. VCOM A common amplifier to set output voltage in a range of 0.3 V to Vo1-0.3 V. Timer latch An output short protection circuit. If at least one output is down after the DC/DC2 and positive/negative charge pump outputs all rise, all the outputs will be shut down.
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7/17
2009.07 - Rev.B
BD81666EFV
Technical Note
Start-up Sequence The DC/DC converter of this IC incorporates a soft start function, and the charge pump incorporates a delay function, for which independent time settings are possible through external capacitors. As the capacitance, 0.001 F to 0.1 F is recommended. If the capacitance is set lower than 0.001 F, the overshooting may occur on the output voltage. If the capacitance is set larger than 0.1 F, the excessive back current flow may occur in the internal parasitic elements when the power is turned OFF and it may damage IC. When the capacitor more than 0.1 F is used, be sure to insert a diode to VCC in series, or a bypass diode between the SS and VCC pins.
Bypass diode Back current prevention diode
VCC
Fig.26 Example of Bypass Diode Use When there is the activation relation (sequences) with other power supplies, be sure to use the high-precision product (such as X5R). Soft start time may vary according to the input voltage, output loads, coils, voltage, and output capacitance. Be sure to verify the operation using the actual product. A delay of the charge pump starts from a point where Vo1 reaches 80% (Typ.).
Soft start time of DC/DC converter block: tss Tss = (Css 0.7 V) / 10 A [s] Where, Css is an external capacitor. Delay time of charge pump block: t DELAY t DELAY = (Css 0.65) / 5 A [s] Where, Css is an external capacitor.
Startup example
VCC
(Input)
IG
(Input)
Vo1
DC/DC (output)
80% DL1
VDD
DC/DC (output 2)
DL2
Vo2GS
(Gate shooting output)
DL3
VGL
(Negative charge pump output)
DL4
DL1 = SS1 capacitance delay time DL2 = SS2 capaciance delay time DL3 = SS3 capacitance delay time DL4 = SS4 capacitance delay time Fig. 27
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8/17
2009.07 - Rev.B
BD81666EFV
Technical Note
Selecting Application Components (1) Output LC constant The inductance L to use for output is decided by the rated current ILR and input current maximum value IOMAX of the inductance. Vin IL IL + IL/2 should not reach the rated value level M1 II IL ton T t Fig. 28 Fig.29 ILR IL M2 D1 IL Vo L M0 D2 M1 ON M1 OFF
Co
Adjust so that IL+IL/2 does not reach the rated current value ILR. At this time, IL and IL can be obtained by the following equation. IL= (1 + Vo Vin ) Iox 1 [A] (:efficiency)
IL= 1 {VinxVo / (Vin + Vo)} x 1 [A] L f Set with sufficient margin because the inductance L value may have the dispersion of 30%. For the capacitor C to use for the output, select the capacitor which has the larger value in the ripple voltage VPP permissible value and the drop voltage permissible value at the time of sudden load change. Output ripple voltage is decided by the following equation. IL Io )RESR + ( Vin / (Vin + Vo)) x VPP = (IL 2 Co
1 f
Perform setting so that the voltage is within the permissible ripple voltage range. For the drop voltage VDR during sudden load change, please perform the rough calculation by the following equation. VDR = I Co x 10 sec [V]
However, 10 s is the rough calculation value of the DC/DC response speed. Make Co settings so that these two values will be within the limit values.
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9/17
2009.07 - Rev.B
BD81666EFV
Technical Note
(2) Output LC constant The inductance L to use for output is decided by the rated current ILR and input current maximum value IOMAX of the inductance. VCC
IL
IOMAX + IL should not reach the rated value level
ILR IOMAX mean current
IL L Co
Vo
t
Fig. 28
Fig. 29
Adjust so that IOMAX + IL does not reach the rated current value ILR. At this time, IL can be obtained by the following equation. 1 Vo 1 IL = (Vcc - Vo) [A] L Vcc f Set with sufficient margin because the inductance L value may have the dispersion of 30%. For the capacitor C to use for the output, select the capacitor which has the larger value in the ripple voltage VPP permissible value and the drop voltage permissible value at the time of sudden load change. Output ripple voltage is decided by the following equation. IL Vo 1 IL RESR + VPP = 2Co Vcc f
[V]
Perform setting so that the voltage is within the permissible ripple voltage range. For the drop voltage VDR during sudden load change, please perform the rough calculation by the following equation. I VDR = 10 s [V] Co However, 10 s is the rough calculation value of the DC/DC response speed. Make Co settings so that these two values will be within the limit values.
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10/17
2009.07 - Rev.B
BD81666EFV
Technical Note
(3) Phase compensation Phase Setting Method The following conditions are required in order to ensure the stability of the negative feedback circuit. Phase lag should be 150 or lower during gain 1 (0 dB) (phase margin of 30 or higher). Because DC/DC converter applications are sampled using the switching frequency, the overall GBW should be set to 1/10 the switching frequency or lower. The target application characteristics can be summarized as follows: Phase lag should be 150 or lower during gain 1 (0 dB) (phase margin of 30 or higher). The GBW at that time (i.e., the frequency of a 0-dB gain) is 1/10 of the switching frequency or below. In other words, because the response is determined by the GBW limitation, it is necessary to use higher switching frequencies to raise response. One way to maintain stability through phase compensation involves canceling the secondary phase lag (-180) caused by LC resonance with a secondary phase advance (by inserting 2 phase advances). The GBW (i.e., the frequency with the gain set to 1) is determined by the phase compensation capacitance connected to the error amp. Increase the capacitance if a GBW reduction is required. (a) Standard integrator (low-pass filter) (b) Open loop characteristics of integrator
A Gain [dB]
(a) -20 dB/decade GBW(b)
Feedback R
A FB C
COMP
0 F 0 Phase -90 [] -180 -90 Phase margin -180 F
Fig. 30
Fig. 31
Point (a)
fa =
1 2RCA
[Hz]
Point (b)
fb = GBW =
1 2RC
[Hz]
The error amp performs phase compensation of types (a) and (b), making it act as a low-pass filter. For DC/DC converter applications, R refers to feedback resistors connected in parallel. From the LC resonance of output, the number of phase advances to be inserted is two. LC resonant frequency fp =
R1 C1 R3
Vo C2 CO MP
1 2LC 1 2C1R1 1 2C2R3
[Hz]
Phase advance
fz1 =
[Hz]
R2
A
Phase advance Fig. 32
fz2 =
[Hz]
Set a phase advancing frequency close to the LC resonant frequency for the purpose of canceling the LC resonance.
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11/17
2009.07 - Rev.B
BD81666EFV
Technical Note
(4) Short protection of timer latch type If the overcurrent protection function operates after all the outputs are stable, all the outputs will be shut down by the latch function. The latch timing is determined by the capacitance connected to the SCP pin. As the capacitance, 0.001 F to 0.1 F is recommended. A startup failure may result if the capacitance is 0.001 F or below. The internal elements may be damaged because an overcurrent state will continue if the capacitance is 1 F or above. t scp = (Cscp 0.6 V) / 5 A [s] Where, Css is an external capacitor. (5) Fault function This IC incorporates a fault function to tell the operating situation of the protection circuit. If the protection circuit turns on, the fault pin will be pulled up by external pull-up resistance, and high-level voltage will be output. In a stable operation state, the output will be low-level voltage. As the resistance value, 10 k to 220 k is recommended. Offset voltage due to the internal on resistance will be generated if the resistance is set to 10 or below. In that case, no low-level voltage may be output correctly. No high-level voltage may be output correctly if the resistance is 220 k or over by leak current. The following conditions will set the fault pin to high level. If UVLO operates If TSD operates If OCP operates If SCP operates (6) Common amp VCOM operates in a range between 0.3 V and V01-0.3 V. Usually, use the buffer type shown in (a). To improve the current drive capability, use PNP and NPN transistors as shown in (b). Use the buffer type specified in (a) if the VCOM is not used, and ground the V+ pin. A resistance setting range of 10 k to 100 k is recommended for R3 and R4. If the resistance is set to 10 k or below, the current consumption will increase and the efficiency of power will be degraded. If the resistance is 100 k or above, the input bias current will be 0.1 A (Typ.) and the offset voltage may become great. (a)
V01 R3 V+ VR4
(b)
Vo1 V+ V30k 30k R3 R4 Vo1
+
VCOM
+
VCOM
-
1000uF
-
VCOM
VCOM
R5 1k
VCOM =
R4 R3 + R4
Vo1 [V] The recommended R5 value is approximately 1 k. Fig. 34
Fig. 33
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12/17
2009.07 - Rev.B
BD81666EFV
(7) Design of Feedback Resistance constant Set the feedback resistance as shown below.
Technical Note
Vo1 R1 R2
VDD
Reference voltage 1.25 V
Vo1, VDD =
R1 + R2 R2
1.25
[V]
FB1 FB2
ERR
Fig. 35 (8) Positive-side Charge Pump Settings The IC incorporates a charge pump controller, thus making it possible to generate stable gate voltage. The output voltage is determined by the following equation. As the setting range, 10 k to 330 k is recommended. If the resistor is set lower than 10 k, it causes reduction of power efficiency. If it is set more than 330 k, the offset voltage becomes larger by the input bias current of 0.4 A (Typ.) in the internal error amp.
Vo2 C6 1000 pF to 4700 pF R6
2
Reference voltage 1.25 V
R7
FB3
ERR
Vo2 =
R6 + R7 R7
1.25
[V]
Fig. 36 In order to prevent output voltage overshooting, insert capacitor C6 in parallel with R6. As the capacitance, 1,000 pF to 4,700 pF is recommended. If the capacitance is not within the range, output voltage oscillation may result. By connecting capacitance to the SS3 pin, the rising delay time can be set for the positive-side charge pump output. The delay time is determined by the following equation. If a capacitance outside this range is inserted, output voltage oscillation may result. Delay time of charge pump block t DELAY t DELAY = (CDLS 0.65) / 5 A [s] Where, CDLS is an external capacitor. (9) Negative-side Charge Pump Settings BD8166EFV incorporates a charge pump controller for negative voltage, thus making it possible to generate stable gate voltage. The output voltage is determined by the following equation. As the setting range, 10 k to 330 k is recommended. If the resistor is set lower than 10 k, it causes reduction of power efficiency. If it is set more than 330k, the offset voltage becomes larger by the input bias current of 0.4 A (Typ.) in the internal error amp.
Vo3 C8 1000 pF to 4700 pF R8 R9 FB4
1.25 V
ERR
Vo3 =
-
R8 R9
1.65 + 1.25 V
[V]
VREF29
2.9 V Fig.37
Like the positive-side charge pump, the rise delay time can be set by connecting capacitance to the SS4 pin. In order to prevent output voltage overshooting, insert capacitor C6 in parallel with R6. As the capacitance, 1,000 pF to 4,700 pF is recommended. If a capacitor outside this range is inserted, the output voltage may oscillate.
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13/17
2009.07 - Rev.B
BD81666EFV
Technical Note
Gate Shading Setting Method The IG input signal allows the high-level and low-level control of the positive-side gate voltage. The slope of output can be set by the external RC. The recommended resistance set value is 200 to 5.1 k and the recommended capacitor set value is 0.001 F to 0.1 F. The aggravation of efficiency may be caused if settings outside this range are made. Determine V by referring to the following value. The following calculation equation is used for V. tW V = Vo2GS (1 - exp ()) [V] CR
TIMING STANDARD VALUE
tWL tWH H L PARAMETER SYMBOL MIN IG " L " Time tLH IG " H " H Vo2GS Time tWH 1 18 -- s tWL = 2 us R = 500 * V = 10 V* 1 TYP 2 MAX -- LIMIT UNIT CONDITION
tWL
s
Vo2GS"H" to "L" Voltage difference Vo2GS"L" to "H" Time
V tLH
10
V s
0.1
V
From positive-side charge pump
Vo2 L
Gate Shading
Vo2GS
Gate driver
R GSOUT C
Fig.38 Gate Shading Timing Chart
Control
IC
Fig. 39 6. SS2 9. SCP 34. SS1
I/O Equivalent Circuit Diagram 2. SW2 3. SW2 38. SW1 39. SW1
Vcc PVcc
4. BOOT2 37. BOOT1
REG
10k 50 SW
7. COMP2 33. COMP1
VR 20 Vcc
8. FB2 12. FB3 25. FB4
VREF29 1k
32. FB1
11. FOULT
10k
13. SS3 30. SS4
VREF29 20
14. IG
15. GSOUT
Vo2
16. Vo2GS
Vo2 Vo2
18. C1L 19. C2L 24. C3
Vo1
22. VGH
26. COM
Vcc
27. V-
28. V+
Vcc
35. VREG
Vcc PVcc
BOOT
Fig. 40
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14/17
2009.07 - Rev.B
BD81666EFV
Technical Note
Notes for use 1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated.
2) GND potential Ensure a minimum GND pin potential in all operating conditions. 3) Setting of heat Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4) Pin short and mistake fitting Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by the presence of a foreign object may result in damage to the IC. 5) Actions in strong magnetic field Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction. 6) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. 7) Ground wiring patterns When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring patterns of any external components. 8) Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements. For example, when the resistors and transistors are connected to the pins as shown in Fig. 41, a parasitic diode or a transistor operates by inverting the pin voltage and GND voltage. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements such as by the application of voltages lower than the GND (P substrate) voltage to input and output pins.
Resistor (Pin A) (Pin B) C

Transistor (NPN) B
(Pin B) B C E GND Parasitic elements N (Pin A) Parasitic elements GND

GND P+ N N P N Parasitic elements GND Parasitic elements N P N P+ P+ N P substrate GND P P+

E
Fig. 41 Example of a Simple Monolithic IC Architecture 9) Overcurrent protection circuits An overcurrent protection circuit designed according to the output current is incorporated for the prevention of IC damage that may result in the event of load shorting. This protection circuit is effective in preventing damage due to sudden and unexpected accidents. However, the IC should not be used in applications characterized by the continuous operation or transitioning of the protection circuits. At the time of thermal designing, keep in mind that the current capacity has negative characteristics to temperatures.
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15/17
2009.07 - Rev.B
BD81666EFV
Technical Note
10) Thermal shutdown circuit (TSD) This IC incorporates a built-in TSD circuit for the protection from thermal destruction. The IC should be used within the specified power dissipation range. However, in the event that the IC continues to be operated in excess of its power dissipation limits, the attendant rise in the chip's junction temperature Tj will trigger the TSD circuit to turn off all output power elements. The circuit automatically resets once the junction temperature Tj drops. Operation of the TSD circuit presumes that the IC's absolute maximum ratings have been exceeded. Application designs should never make use of the TSD circuit. 11) Testing on application boards At the time of inspection of the installation boards, when the capacitor is connected to the pin with low impedance, be sure to discharge electricity per process because it may load stresses to the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC.
Power Dissipation POWER DISSIPATION: PD [mW]
5000 4000 300 200 100 0 (4) (3) (2) (1)
On 70 70 1.6 mm glass epoxy PCB
(1) 1-layer board (Backside copper foil area 0 mm 0 mm) (2) 2-layer board (Backside copper foil area 15 mm 15 mm) (3) 2-layer board (Backside copper foil area 70 mm 70 mm) (4) 4-layer board (Backside copper foil area 70 mm 70 mm)
2
5
75 85
100
125
150
AMBIENT TEMPERATURE: Ta [C] Fig. 42
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16/17
2009.07 - Rev.B
BD81666EFV
Ordering part number
Technical Note
B
D
8
Part No.
1
6
6
E
F
V
-
E
2
Part No.
Package HTSSOP-B40
Packaging and forming specification E2: Embossed tape and reel
HTSSOP-B40
13.60.1 (MAX 13.95 include BURR) (8.4)
40 21

4 +6 -4
Tape Quantity
Embossed carrier tape (with dry pack) 2000pcs E2
The direction is the 1pin of product is at the upper left when you hold
0.5 0.15
1.2 0.2
7.80.2
5.40.1
1
0.625
1PIN MARK
20
(3.2)
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
+0.05 0.17 -0.03 S
1.0Max.
0.850.05 0.080.05
+0.05 0.24 -0.04 0.65 0.08 S
0.08
M
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
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17/17
2009.07 - Rev.B
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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